1. Field of the Invention
The present invention relates to a syndrome calculation circuit for, in particular, detecting the beginning of data packets preceded by headers.
2. Discussion of the Related Art
In ATM ("Asynchronous Transfer Mode") networks, the data is transmitted by packets of 53 bytes, called cells. A cell is constituted by a 5-byte header which indicates, in particular, the destination of the data and a 48-byte payload.
FIG. 1 shows such a header. The header includes four first bytes A1 to A4 followed by an HEC ("Header Error Control") byte for detecting and correcting errors in the first four bytes of the header. The header is used in particular for determining the position of the cells in a continuous data flow. To form the HEC byte at transmission, the following polynomial is first formed: EQU b.sub.1 x.sup.31 +b.sub.2 x.sup.30 + . . . +b.sub.31 x+b.sub.32
where b.sub.1 to b.sub.32 are the bits of bytes A1 to A4. This polynomial is multiplied by polynomial x.sup.8 and then divided by a polynomial called a generator polynomial of degree 8. The remainder of the division is a polynomial of degree 7, whose coefficients b.sub.33 to b.sub.40 are the bits of byte HEC.
At the reception level, coefficients b.sub.1 to b.sub.40 constitute a polynomial of degree 39 which is divided by the generator polynomial. The remainder of this division, called the syndrome, is zero if the transmission was error-free. According to the non-zero value of the syndrome, a double error is detected or a single error is corrected.
FIG. 2 shows an example of a conventional circuit, called Linear Feedback Shift Register (LFSR), which is used to calculate the syndromes. This LFSR circuit is constructed according to the generator polynomial, which, in this case, is EQU x.sup.8 +x.sup.2 +x+1
This polynomial is the polynomial generally used in ATM networks for calculating byte HEC.
The LFSR circuit includes 8 flip-flops S1 to S8, respectively corresponding to coefficients S1 to S8 of the syndrome, connected in a ring. Thus, each flip-flop receives the output of the preceding flip-flop and the first flip-flop S1 receives the output of the last flip-flop S8. Besides, flip-flop S1 is preceded by an adder 10 which receives the output of flip-flop S8 and the successive bits to analyze b.sub.1 to b.sub.40. Flip-flops S2 and S3 are preceded by respective adders 11 and 12, each of which receives the output of the preceding flip-flop and the output of flip-flop S8. Adders 10 to 12 are XOR gates in practice.
Initially, flip-flops S1 to S8 are at zero. They are then enabled at each arrival of a bit b of the header to analyze. When the fortieth bit b.sub.40 has arrived, flip-flops S1 to S8 contain the syndrome coefficients. Once the syndrome has been exploited, the flip-flops are reset and enabled anew to calculate the syndrome of a new header.
In asynchronous networks, such as ATM networks, the reception circuits have to be synchronized on the data cells. For this purpose, the fact that the syndrome is zero for the headers can be utilized. An LFSR circuit is then reset after each 40-bit packet to analyze the following 40-bit packet. If the headers are aligned with the 40-bit packets, a zero syndrome is finally found when a header is analyzed.
However, the headers are not very likely to be aligned with the analyzed 40-bit packets. Thus, if no zero syndrome has been found after a cell length, the analysis has to be shifted by skipping bits in the data flow (after analyzing the last packet of the cell length, one or several bits are allowed to pass before resuming the analysis). By operating so, an alignment of the analyzed packets with the headers is obtained after at most 40 cells. Thus, there is a risk of losing 40 cells at the beginning of a transmission.
To avoid this drawback, one could provide 40 LFSR circuits each analyzing one 40-bit packet shifted by one bit with respect to the packet analyzed by the preceding circuit. This solution is very costly in terms of surface area and power consumption.
Moreover, an LFSR circuit is unable, in present common technologies (CMOS), to process bits arriving at the transmission speeds currently required in ATM networks, that is, speeds which can reach 622 megabits per second.